Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask will generally contain a circuit pattern corresponding to an individual layer of the IC, and a projection beam of radiation will be used to image this pattern onto various target portions on a substrate (e.g., a silicon wafer) that has been coated with a layer of radiation-sensitive material (e.g., resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated, one at a time. In one type of lithographic apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern through the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. More information with regard to lithographic apparatus as here described can be obtained, for example, from U.S. Pat. No. 6,046,792, the entire contents of which is hereby incorporated by reference.
Lithographic apparatus may employ various types of projection radiation, non-limiting examples of which include ultra-violet light (“UV”) radiation (e.g., with a wavelength of 365 nm, 248 nm, 193 nm, 157 nm or 126 nm), extreme UV (“EUV”), X-rays, ion beams or electron beams. Depending on the type of radiation used and the particular design requirements of the apparatus, it may include a projection system having refractive, reflective or catadioptric components, and include vitreous elements, grazing-incidence mirrors, selective multi-layer coatings, magnetic and/or electrostatic field lenses, etc; for simplicity, such components may be loosely referred to, either singly or collectively, as a “lens”.
In a manufacturing process using such a lithographic projection apparatus, a pattern in a mask is imaged onto a wafer which is at least partially covered by a layer of resist. Prior to this imaging step, the wafer may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the wafer may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an integrated circuit (IC). Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the wafer. These devices are then separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes may be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997 ISBN 0-07-067250-4.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
Furthermore, the constant improvements in microprocessor speed, memory packing density and low power consumption for micro-electronic components are directly related to the ability of lithography techniques to transfer and form patterns onto the various layers of a semiconductor device. The current state of the art requires patterning of CD's well below the available light source wavelengths. For instance the current production wavelength of 248 nm is being pushed towards patterning of CD's smaller than 100 nm. This industry trend will continue and possibly accelerate in the next 5-10 years, as described in the International Technology Roadmap for Semiconductors (ITRS 2000).
Lithographic methods aimed at improving resolution, while retaining acceptable process latitude and robustness, are classified as Resolution Enhancement Techniques (RET's) and include a very wide range of applications. Examples include: light source modifications (e.g., Off-Axis Illumination), use of special masks, which exploit light interference phenomena (e.g., Attenuated Phase Shift Masks, Alternating Phase Shift Masks, Chromeless Masks, etc.), and mask layout modifications (e.g., Optical Proximity Correction).
In an Off-Axis illumination regimen, as illustrated in FIG. 1, increased focus latitude and image contrast are achieved by capturing at least one of the first orders of the pattern spatial frequencies. As shown in FIG. 1, a typical off-axis illumination system includes in-part a light source 11, a mask 12, a lens 13 and the wafer 14 covered with photoresist. With dipole illumination, the light source is confined to two poles, in order to create the conditions for two-beam imaging with theoretical infinite contrast. FIG. 2 illustrates the basic principles of dipole imaging. As shown, a dipole illumination system includes in-part a dipole aperture 16 (or other dipole generating means, such as a suitable diffractive optical element), a condenser lens 17, a mask 18, a projection lens 19 and the wafer 20. The dipole apertures 16 can be of various shapes and orientations, e.g., horizontal, vertical or at any given angle. Exemplary dipole apertures 16 of various sizes and shapes are shown in FIGS. 3(a)-3(h).
When dipole illumination is used, resolution is enhanced only for geometrical patterns with orientations perpendicular to the pole orientation axis. For example, a “horizontal” dipole allows the patterning of sub-resolution “vertical” lines or spaces; the terms “vertical” and “horizontal” refer to a set of orthogonal directions in the plane of the geometrical pattern. In a typical dipole application for a layout comprising both horizontal and vertical critical patterns, two exposures are needed with two orthogonal dipole sources, one for each exposure.
As the demand for cheaper, faster, lower power consuming integrated circuits increases, so must the device packing density of the IC. Minimizing transistor dimensions is of paramount importance to the advancement of semiconductor technologies. Minimizing transistor dimensions allows more transistors to be formed in a given area. Minimizing the dimensions also allows the transistors to operate at higher speeds. The ability to place more high speed transistors in an IC allows more complex and sophisticated functionality to be incorporated into the IC device. Therefore, as a result of reducing the size of transistors in an IC, and improving the speed of the IC, products which use these IC's, such as, for example, home computers, will be able to operate faster and with greater functionality than ever before.
Increasing the device packing density of an IC by minimizing transistor dimensions inherently requires that the interconnect technology used to couple transistors together be similarly minimized. In a typical interconnect technology scheme, after transistors are formed on a semiconductor substrate, a layer of dielectric material is used to coat the surface of the transistors to physically and electrically insulate them. Once this dielectric material is deposited, openings are etched through the dielectric material to the underlying semiconductor substrate. Conductive material is deposited into these openings in order to make electrical contact to the substrate surface. These openings filled with conductive material are called contacts.
Once a first layer of interconnects has been deposited on the surface of the first dielectric layer, a second dielectric layer is deposited to coat the surface of this first interconnect layer. Openings are then etched into this second dielectric layer to permit electrical coupling to the first interconnect layer by filling these openings with conductive material. These openings filled with conductive material are called vias. Once the interconnects of the second interconnect layer have been formed, a third dielectric layer is deposited to coat the second interconnect layer, and vias are again formed in the third dielectric layer. This process of forming an interconnect layer, coating with a dielectric layer, forming vias in the dielectric layer, and forming another interconnect layer on its surface may be repeated any number of times in IC manufacturing technology.
The dimensions of these contacts and vias have historically been limited by the photolithographic technology used to define the size and location of contact and via openings. For example, conventional photolithographic technologies are currently capable of defining, or “resolving”, an opening having a minimum width of approximately 100 nanometers (nm). This minimum resolvable dimension significantly limits the device packing density of the IC.
Accordingly, there is a need in the art for a method of patterning contact holes with openings less than 100 nm. Additionally, it would be advantageous to produce masks for such contact holes that are simpler to manufacture, thereby decreasing costs.